Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 26)

2–18 Chapter 2: Board Components
Configuration, Status, and Setup Elements
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
■ JTAG programming header (J61) is used for configuring the FPGA using an
external USB-Blaster (not supplied) and the Quartus II Programmer.
The following sections describe each of these methods.
Embedded USB-Blaster
Figure 2–4 shows the block diagram for the embedded USB-Blaster. The USB-Blaster
is implemented using a USB Type-B connector (J60), a Future Technologies FT245BL
USB PHY device (U79), and an Altera EPM240M100C4N MAX II CPLD. This allows
the configuration of the FPGA using a USB cable directly connected between the USB
port on the board and a USB port of a PC running the Quartus II software.
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain at the JTAG programming header (J61).
Fast Passive Parallel Download
Figure 2–5 shows the block diagram for the MAX II+Flash FPP configuration. This
method is used for automatic configuration of the FPGA upon board power-up or
reset with the configuration programming image stored in the flash memory. The FPP
download controller is implemented within an Altera EPM240M100C4N MAX II
CPLD (U72). This CPLD controller, together with the Numonyx PC28F00AM29EWL
1-Gb CFI NOR-type flash memory (U65), performs the FPP configuration upon board
power-up or reset. The CPLD shares the flash interface with the FPGA. The
configuration program select push-button, PGM_SEL, (S10) selects between two .pof
files (factory or user) stored in the flash. The FPP controller uses the Altera Parallel
Flash Loader (PFL) megafunction to configure the FPGA by reading data from the
flash and converting it to FPP format. This data is written to the FPGA’s dedicated
configuration pins during configuration.
Figure 2–4. Embedded USB-Blaster
USB Type-B
Connector
(J60)
FTDI
FT245BL
USB PHY
(U79)
USB FIFO BUS EPM240M
MAX II
CPLD JTAG
JT
A
G
JTAG Programming
Header (J61)
USB
Stratix IV GT
FPGA (U44)