Data pattern settings, Data pattern settings -14 – Altera Transceiver SI User Manual
Page 22
2–14
Getting Started User Guide
Altera Corporation
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
June 2006
Test the Transceiver Performance Using Pre-Defined Designs
■
COM Port #
—When the driver is installed, the COM Port values are
listed under Ports (COM and LPT) in the Windows Device Manager
window (go to Start > Control Panel > Administrative Tools >
Computer Management
> Device Manager). See
Figure 2–5
. The
highest COM port number listed under Ports (COM and LPT) is
required to be used in the COM Port # box.
■
Open Link
and Close Link—When you click Open Link or Close
Link,
the link with the board and the status of the connection is
shown under Display Adapters in the Device Manager window (see
Figure 2–5
).
Figure 2–5. Device Manager Window
1
When the SOF is downloaded to the hardware, the link from the
GUI to the board should be closed.
Data Pattern Settings
The top center of the control panel window provides the following Data
Pattern
settings:
■
Ch0 Pattern
■
Ch1., Ch4 Pattern
■
Ch5 Pattern
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)