Analog settings, Analog settings -12 – Altera Transceiver SI User Manual
Page 20
2–12
Getting Started User Guide
Altera Corporation
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
June 2006
Test the Transceiver Performance Using Pre-Defined Designs
Figure 2–3. Demo Application Control Panel WIndow
1
Before walking through the GUI tutorial, you should configure
the Stratix II GX device with one of the pre-defined SOFs listed
in
Table 2–3
.
Analog Settings
The left side of the control panel window provides the physical media
attachment sublayer (PMA) setting values that represent the different
transceiver Quads and are based on the VCCHTX setting. The VCCHTX
setting should correspond with jumper header (J50) settings. See
Table 2–5
.
Table 2–5. Jumper Header (J50) Connections and VCCHTX Values
Jumper Header (J50) Connection
VCCHTX
Pins 1 and 2
1.5 V
Pins 2 and 3
1.2 V
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
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- Cyclone III FPGA Starter Kit (36 pages)
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- Stratix V Avalon-ST (293 pages)
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