Altera PowerPlay Early Power Estimator User Manual
Page 28
Column Heading
Description
RAM Mode
Select from the following modes:
• Single-Port
• Simple Dual-Port
• True Dual-Port
• ROM
The mode is based on how the Quartus II Compiler implements the
RAM. If you are unsure how your memory module is implemented,
Altera recommends compiling a test case in the required configuration
in the Quartus II software. You can find the RAM mode in the Mode
column of the Quartus II Compilation Report. In the Compilation
Report, select Fitter and click Resource Section. Click RAM
Summary.
A single-port RAM has one port with a read and write control signal. A
simple dual-port RAM has one read port and one write port. A true
dual-port RAM has two ports, each with a read and write control
signal. ROMs are read-only single-port RAMs.
Port A–Clock Freq (MHz)
Enter the average percentage of time the input clock enable for Port A
is active, regardless of the activity on the RAM data and address inputs.
The enable percentage ranges from 0 to 100%. The default value is
25%.
RAM power is primarily consumed when a clock event occurs. Using a
clock enable signal to disable a port when no read or write operation is
occurring can result in significant power savings.
Port A–Write %
Enter the average percentage of time Port A of the RAM block is in
write mode versus read mode. For simple dual-port (1R/1W) RAMs,
the write Port A is inactive when not executing a write operation. For
single-port and dual-port RAMs, Port A reads when it is not written to.
This field is ignored for RAMs in ROM mode.
This value must be a percentage number between 0 and 100%. The
default value is 50%.
Port B–Clock Freq (MHz)
Enter the clock frequency for Port B of the RAM blocks in MHz. This
value is limited by the maximum frequency specification for the RAM
type and device family. Port B is ignored for RAM blocks in ROM or
single-port mode or when the chosen RAM type is MLAB.
Port B–Enable %
Enter the average percentage of time the input clock enable for Port B
is active, regardless of the activity on the RAM data and address inputs.
The enable percentage ranges from 0 to 100%. The default value is
25%. Port B is ignored for RAM blocks in ROM or single-port mode or
when the chosen RAM type is MLAB.
RAM power is primarily consumed when a clock event occurs. Using a
clock-enable signal to disable a port when no read or write operation is
occurring can result in significant power savings.
3-18
RAM Worksheet
UG-01070
2015.01.20
Altera Corporation
PowerPlay Early Power Estimator Worksheets