Altera DSP Development Kit, Stratix V Edition - Manual (Page 51)

July 2013 Altera Corporation DSP Development Kit, Stratix V Edition
User Guide
A. Programming the Flash Memory
Device
As you develop your own project using the Altera tools, you can program the flash
memory device so that your own design loads from flash memory into the FPGA on
power up. This appendix describes the preprogrammed contents of the common flash
interface (CFI) flash memory device on the Stratix V GS development board and the
Nios II EDS tools involved with reprogramming the user portions of the flash
memory device.
The Stratix V GS development board ships with the CFI flash device preprogrammed
with a default factory FPGA configuration for running the Board Update Portal
design example and a default user configuration for running the Board Test System
demonstration. There are several other factory software files written to the CFI flash
device to support the Board Update Portal. These software files were created using
the Nios II EDS, just as the hardware design was created using the Quartus II
software.
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For more information about Altera development tools, refer to the Design Software
page of the Altera website.
CFI Flash Memory Map
Table A–1 shows the default memory contents of two interlaced 512-Mbyte CFI flash
devices. Each flash device has a 16-bit data bus and the two combined flash devices
allow for a 32-bit flash memory interface.
For the Board Update Portal to run correctly and update designs in the user memory,
this memory map must not be altered.
Table A–1. Byte Address Flash Memory Map
Block Description Size (KB) Address Range
Board test system scratch 256 0x07FC.0000 - 0x07FF.FFFF
User software 14,336 0x071C.0000 - 0x07FB.FFFF
Factory software 8,192 0x069C.0000 - 0x071B.FFFF
zipfs (html, web content) 8,192 0x061C.0000 - 0x069B.FFFF
User hardware 2 33,280 0x0414.0000 - 0x061B.FFFF
User hardware 1 33,280 0x020C.0000 - 0x0413.FFFF
Factory hardware 33,280 0x0004.0000 - 0x020B.FFFF
PFL option bits 64 0x0003.0000 - 0x0003.FFFF
Board information 64 0x0002.0000 - 0x0002.FFFF
Ethernet option bits 64 0x0001.0000 - 0x0001.FFFF
User design reset vector 64 0x0000.0000 - 0x0000.FFFF