Altera DSP Development Kit, Stratix V Edition - Manual (Page 40)

6–16 Chapter 6: Board Test System
Using the Board Test System
DSP Development Kit, Stratix V Edition July 2013 Altera Corporation
User Guide
The XCVR2 Tab
The XCVR2 tab allows you to perform loopback tests on the QSFP, HSMB
Transceivers, and HSMB Parallel interfaces.
Figure 6–8 shows the XCVR2 tab.
1
You must have the loopback HSMC installed on the HSMC port B connector that you
are testing for this test to work correctly. Unless you have a QSFP loopback module,
you will need test the QSFP in the internal loopback mode (serial loopback = 1).
The following sections describe the controls on the XCVR2 tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded, and all TX and RX PLL lanes are
phase locked to data; RX lanes are word aligned and deskewed.
Figure 6–8. The XCVR2 Tab