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Clock Control Block IP Core
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Altera Clock Control Block IP Core User Manual
Altera Measuring instruments
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Altera Clock Control Block IP Core User Manual | 26 pages
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Table of contents
Document Outline
Contents
1. About this Megafunction
Features
Device Support
2. Parameter Settings
MegaWizard Parameter Settings
Command Line Interface Parameters
3. Functional Description
Clock Control Block
Global Clock Control Block
Regional Clock Control Block
External PLL Output Clock Control Block
Clock Enable Signals
Single Register Clock Enable Circuit
Double Register Clock Enable Circuit
Clock Enable Timing
Connectivity Restrictions
General Restrictions
ALTCLKCTRL Megafunction Ports
Input Ports
Output Ports
Prototypes and Component Declarations
Verilog HDL Prototype
VHDL Component Declaration
VHDL LIBRARY-USE Declaration
Additional Information
Document Revision History
How to Contact Altera
Typographic Conventions
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