Altera Clock Control Block IP Core - Manual (Page 13)

February 2014 Altera Corporation Clock Control Block (ALTCLKCTRL) Megafunction
User Guide
3. Functional Description
This chapter describes the functional description and the design examples of the
ALTCLKCTRL megafunction. This section also includes the prototype, component
declarations, and the ports descriptions of the ALTCLKCTRL megafunction. You can
use the ports to customize the ALTCLKCTRL megafunction according to your
application.
Clock Control Block
A clock control block is a dynamic clock buffer that allows you to enable and disable
the clock network and dynamically switch between multiple sources to drive the
clock network.
Table 3–1 shows the clock control block and the devices that support it.
The following table describes the clock control block.
Table 3–1. Clock Buffers that Drive the Clock Control Block
Clock Control
Block
Arria 10 Arria V Arria II GX Stratix V Stratix IV Stratix III Cyclone V Cyclone IV Cyclone III
Global Clock
Network
v v v v v v v v v
Dual Regional
Clock Network
— v v v v v v — —
Regional Clock
Network
v v v v v v v — —
Dedicated
External Clock
Out Path
v v v v v v v v v
For Periphery
Clock
v v v v v v v — —
Table 3–2. Clock Control Block
Clock Control Block Description
Global Clock Network
Allows a clock signal (or other global signals) to
reach all parts of the chip with a similar amount
of skew.
Regional Clock Network
Allows a signal to reach one quadrant of the chip
(though half of the chip can be reached by
driving two quadrants).
For Arria 10 devices, the regional clock network
drives a “sliding window” of SCLK regions
corresponding to six interface tiles high.
External Clock-Out Path
Represents the clock path from the outputs of
the phase-locked loop (PLL) to the dedicated
PLL_OUT pins. The ALTCLKCTRL megafunction
also provides glitch-free implementation for
multiple clock input signals.