Altera Clock Control Block IP Core - Manual (Page 18)

3–6 Chapter 3: Functional Description
Connectivity Restrictions
Clock Control Block (ALTCLKCTRL) Megafunction February 2014 Altera Corporation
User Guide
■ When you are using multiple input sources, the inclk[]ports can only be driven
by the dedicated clock input pins and the PLL clock outputs. Dedicated clock
input pins must feed only inclk[0] and inclk[1], while the PLL clock outputs
must feed only inclk[2] and inclk[3].
■ If the clock control block feeds any inclk[] port of another clock control block,
both must be able to be reduced to a single clock control block of equivalent
functionality.
■ When you are using the glitch free switchover feature, the clock you are switching
from must be active. If it is not active, the switchover circuit will not be able to
transition from the clock you originally selected.