Altera Arria V GX FPGA - Manual (Page 41)

Chapter 6: Board Test System 6–19
Using the Board Test System
July 2012 Altera Corporation Arria V GX FPGA Development Kit
User Guide
The SDI/Bullseye Tab
The SDI/Bullseye tab ( Figure 6–8 ) allows you perform loopback tests on the Bull’s
Eye and SDI ports.
The following sections describe the controls on the SDI/Bullseye tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Figure 6–8. The SDI/Bullseye Tab