Altera Arria V GT FPGA - Manual (Page 50)

6–28 Chapter 6: Board Test System
Samtec High-speed Bull’s Eye Connector
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
5. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
1 Using the Quartus II programmer to configure a device on the board causes other
JTAG-based applications such as the Board Test System and the Power Monitor to lose
their connection to the board. Restart those applications after configuration is
complete.
Samtec High-speed Bull’s Eye Connector
This kit has a Samtec Bull’s Eye connector with transceivers and a clock output from
the clock buffer (U25).
f For details on the pinout, refer to the Arria V GT FPGA Development Board Reference
Manual .
f For details on how to use the Bull’s Eye interface, refer to the Altera Arria V GX FPGA
Development Kits page on the Samtec website.
For information on how to install the cable using the cable tool, refer to the
bullyseye-instructions.pdf
file that resides in the
\kits\arriaVGT_5agtfd7kf40_fpga\documents. directory.