Altera Arria V GT FPGA - Manual (Page 32)

6–10 Chapter 6: Board Test System
Using the Board Test System
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
Port (FPGA1)
The Port (FPGA1) control allows you to specify which interface to test . The following
port tests are available.
Design run at 10 Gbps:
■ XCVR x4
Design run at 50 Mbps:
■ CMOS x3
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters (at
50MHz) that affect the active transceiver interface. The following settings are
available for analysis:
■ Serial Loopback —Routes signals between the receiver and the transmitter. Enter
the following values to enable the serial loopbacks:
0 = high speed serial transceiver signals to loopback on the board
1 = serial loopback
2 = reverse serial loopback pre-CDR
4 = reverse serial loopback post-CDR
■ VOD —Specifies the voltage output differential of the transmitter buffer.
■ Pre-emphasis tap
■ Pre —Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
■ First post —Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
■ Second post —Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
■ Equalizer —Specifies the setting for the receiver equalizer.
■ DC gain —Specifies the DC portion of the receiver equalizer.
Data Type
The Data type control specifies the type of data contained in the transactions for
transceivers. The LVDS design uses PRBS8, and the CMOS design uses PRBS3. The
following data types are available for transceiver analysis:
■ PRBS7 —Selects pseudo-random 7-bit sequences.
■ PRBS15 —Selects pseudo-random 15-bit sequences.
■ PRBS23 —Selects pseudo-random 23-bit sequences.
■ PRBS31 —Selects pseudo-random 31-bit sequences.
■ HF1 —highest frequency divide-by-2 data pattern 10101010.
■ HF2 —next highest frequency divide-by-4 data pattern 1100110011001100.
■ HF3 —second lowest frequency divide-by-8 data pattern 1111000011110000.