Altera Arria V GT FPGA - Manual (Page 30)

6–8 Chapter 6: Board Test System
Using the Board Test System
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
The following sections describe the controls on the Flash tab.
Read
The Read control reads the flash memory on your board. To see the flash memory
contents, type a starting address in the text box and click Read. Values starting at the
specified address appear in the table. The flash memory addresses display in the
format the Nios II processor within the FPGA uses, that is, each flash memory address
is offset by 0x0800.0000. Valid are entries are 0x0000.0000 through 0x07FF.FFFF.
1 If you enter an address outside of the flash memory address space, a warning
message identifies the valid flash memory address range.
Write
The Write control writes the flash memory on your board. To update the flash
memory contents, change values in the table and click Write. The application writes
the new values to flash memory and then reads the values back to guarantee that the
graphical display accurately reflects the memory contents.
1 To prevent overwriting the dedicated portions of flash memory, the application limits
the user-writable flash memory address range to the uppermost 128 KB memory
block, as shown in
Figure 6–1 on page 6–1 and Table A–1 on page A–1 ).
Random Test
Starts a random data pattern test to flash memory, which is limited to a scratch page in
the upper 128K block.
CFI Query
The CFI Query control updates the memory table, displaying the CFI ROM table
contents from the flash device.
Increment Test
Starts an incrementing data pattern test to flash memory, which is limited to a scratch
page in the upper 128K block.
Reset
The Reset control executes the flash device’s reset command and updates the memory
table displayed on the Flash tab.
Erase
Erases flash memory, which is limited to a scratch page in the upper 128K block.
Flash Memory Map
Displays the flash memory map for the Arria V GT FPGA Development Kit.