Altera Arria V GT FPGA - Manual (Page 35)

Chapter 6: Board Test System 6–13
Using the Board Test System
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Port (FPGA1)
The Port (FPGA1) control allows you to specify which interface to test . The following
port tests are available.
■ Chip to Chip XCVR x8 (HSMA design run at 6.4 Gbps)
Designs run at 10 Gbps:
■ SMA (GXB_L11)
■ SFP_A (GXB_L9)
■ SFB_B (GXB_L14)
■ Bull’s Eye (GXB_L15)
■ Bull’s Eye (GXB_R16)
■ Bull’s Eye (GXB_R17)
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
■ Serial Loopback —Routes signals between the receiver and the transmitter. Enter
the following values to enable the serial loopbacks:
0 = high speed serial transceiver signals to loopback on the board
1 = serial loopback
2 = reverse serial loopback pre-CDR
4 = reverse serial loopback post-CDR
■ VOD —Specifies the voltage output differential of the transmitter buffer.
■ Pre-emphasis tap
■ Pre —Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
■ First post —Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
■ Second post —Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
■ Equalizer —Specifies the setting for the receiver equalizer.
■ DC gain —Specifies the DC portion of the receiver equalizer.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS7 —Selects pseudo-random 7-bit sequences.
■ PRBS15 —Selects pseudo-random 15-bit sequences.