Altera Advanced SEU Detection IP Core User Manual
Page 7
Figure 5: Altera Advanced SEU Detection Core Signals for Off-Chip Processing
clk
reset
cache_comparison_off
data
valid
error
data
valid
ready
error
cache_fill_level
critical_error
clk
reset
cache_comparison_off
emr[66:0]
emr_valid
emr_error
cache_data[34:0]
cache_valid
cache_ready
cache_error
cache_fill_level[3:0]
critical_error
my_asd
Altera Advanced SEU Detection IP Core
Table 3: Altera Advanced SEU Detection Core Signals for Off-Chip Processing
Interface
Signals
Type
Width
Description
Clock and reset
clk
Input
1
• Clock input.
• Recommended frequency is 100 MHz or
higher.
reset
Input
1
Active-high reset.
Cache Configu‐
ration
cache_comparison_off
Input
1
• Static input signal.
• Commands the IP core to bypass cache
comparison.
• You can use this signal with the internal
scrubbing feature for custom design.
Avalon-ST
(Streaming)
Sink Interface
Signals
(2)
emr
Input
67
Error Message Register data input from the
Altera Error Message Register Unloader IP
core.
emr_valid
Input
1
Indicates when emr data input is valid.
emr_error
Input
1
• Indicates when emr data will be ignored due
to an error.
• This may occur when there is a data overrun
from the Altera EMR Unloader IP core.
Errors Output
critical_error
Outpu
t
1
Indicates that an SMH lookup determined that
the EDCRC error is in a critical region.
(2)
The Avalon (ST) Streaming Sink Interface should be connected to the corresponding Avalon-ST Source
Interface of the EMR Uploader IP Core.
ALTADVSEU
2015.05.04
Off-Chip Processing Signals
7
Altera Advanced SEU Detection IP Core User Guide
Altera Corporation