Altera Advanced SEU Detection IP Core - Manual (Page 5)

Off-Chip Lookup Sensitivity Processing
The Altera Advanced SEU Detection IP core interprets the content of the error detection block’s EMR
and presents information to a system processor, which determines whether the failure affects the device
operation. The system processor implements the algorithm to perform a lookup against the .smh .
The off-chip lookup sensitivity processing consists of two components:
• Design logic to interpret content of the EMR of the CRC block and present the information to a
processor interface.
• Cache to store off-loaded content of the EMR.
Figure 3: System Overview for Off-Chip Lookup Sensitivity Processing
EMR
Unloader
IP Core
Advanced
SEU Detection
IP Core
Error Message
Cache Interface
Error Message
Register Interface
CRAM CRC Error Detected
FPGA
Sensitivity Processor
(e.g., System CPU)
CRC_ERROR
Sensitivity Lookup
Information (SMH)
Stored in System Memory
The EMR processing unit interprets the content of EMR offloaded from the CRC block by the EMR
Uploader IP core upon an SEU. The EMR processing unit writes each unique EMR value into cache, until
the cache is full. After the cache is full, it asserts a cache overflow flag to the system interface.
For each new value written into cache, the EMR processing unit asserts an interrupt to the processor. The
system processor reads the EMR value and performs a lookup against the .smh to determine the criticality
of a CRAM location. After the system processor services the interrupt, the EMR processing unit advances
the cache line and generates additional interrupt assertions, provided that there is an EMR value in cache
that has not been processed.
After SMH lookup, the system processor determines the required corrective response.
Related Information
• Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Provides more information about the design security for Stratix IV devices.
• Configuration, Design Security, and Remote System Upgrades in Arria V Devices
Provides more information about the design security for Arria V devices.
• Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Provides more information about the design security for Cyclone V devices.
• Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Provides more information about the design security for Stratix V devices.
ALTADVSEU
2015.05.04
Off-Chip Lookup Sensitivity Processing 5
Altera Advanced SEU Detection IP Core User Guide Altera Corporation
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