Altera Advanced SEU Detection IP Core - Manual

Altera Advanced SEU Detection IP Core User Guide
2015.05.04
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The Altera Advanced SEU Detection IP core contains the following features:
• Hierarchy tagging—Enables tagging of logical hierarchies and specifying their criticality relative to
SEU.
• Sensitivity processing—Determines the criticality of an SEU detected and located by error detection
cyclical redundancy check (EDCRC) hard IP. This feature includes on and off-chip sensitivity
processing.
Table 1: Features Device Family Support
Feature Supported Device
Hierarchy tagging Stratix ® IV, Arria ® V, Arria V GZ, Cyclone ® V, Stratix V and later.
Sensitivity processing Arria V, Arria V GZ,Cyclone V, Stratix V and later.
You can select and configure the Altera Advanced SEU Detection IP core through the IP Catalog and
parameter editor in the Quartus ® II software.
Related Information
Introduction to Altera IP Cores
Functional Description
Stratix IV devices contain a 16-bit cyclic redundancy check (CRC) value per CRAM frame, and Arria V,
Cyclone V, Stratix V, and later device families contain a 32-bit CRC value per CRAM frame. The CRC
value allows the configuration engine to determine the SEU location. The Quartus II software can
generate a Sensitivity Map Header File ( .smh ) of the configuration regions of your design that are sensitive
to SEU.
You can instantiate the Altera Advanced SEU Detection IP core with the following configurations:
• On-Chip Lookup Sensitivity Processing—Error location reporting and lookup performed by the
FPGA.
• Off-Chip Lookup Sensitivity Processing—Error location lookup determined by an external unit (such
as a microprocessor).
On-Chip Lookup Sensitivity Processing
All device families that support SEU detection include a hard error detection block that detects soft errors
and provides the location of single-bit errors, and double-bit adjacent errors for supported devices. The
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