Document revision history – Altera Advanced SEU Detection IP Core User Manual
Page 22
Note: The possible values for
sensitivity_data_tag_size
field are 1,2,4 or 8 that allows to support
a maximal of 255 possible non-zero region masks for a design.
Document Revision History
Table 6: Document Revision History
Date
Version
Changes
May 2015
2015.05.04
• Added note to possible values for sensitivity_data_tag_size
field.
• Updated largest ASD region ID in the Altera Advanced SEU
Detection IP Core Parameters.
• Updated supported device for performing Lookup for
Revision 1 and 2.
• Updated features and device family support by combining
in a table.
• Removed duplicated signals in Off-Chip processing signals
table.
• Updated SMH frame information array description to
reduce redundancies.
June 30 2014
2014.06.30
• Updated supported devices.
• Replaced information about the MegaWizard Plug-in
Manager with the IP Catalog.
December 2012
1.0
Initial release.
22
Document Revision History
ALTADVSEU
2015.05.04
Altera Corporation
Altera Advanced SEU Detection IP Core User Guide
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)