Altera Cyclone III FPGA Starter Kit User Manual
Page 28
A–2
Altera Corporation
Cyclone III FPGA Starter Kit User Guide
July 2010
Creating a Flash-Programmable POF File
2.
Select the following settings:
●
Programming File Type:
Programmer Object File (.pof)
●
Configuration Device:
CFI_128MB
●
Mode:
Active Parallel
●
File Name:
Type the name of the flashable .pof to write
1
If you choose to overwrite the existing .pof, a warning
message occurs.
3.
Under Input file to the convert, select Configuration Master under
SOF Data
. Refer to
.
1
Before moving to the next step, ensure that the setting for
the Configuration Device is CFI_128MB.
Figure A–2. Input File to Convert
4.
Click Add File.
5.
Choose the .sof you want to convert and click OK.
6.
Select SOF Data and click Properties. The SOF Data Properties
window appears.
7.
Select and type the following settings as shown in
Figure A–3
:
●
Pages:
0
●
Address mode for selected pages:
Start
●
Start address (32-bit hexadecimal):
0x020000
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)