Development board and control panel setup, Development board setup, Development board setup –1 – Altera Cyclone III FPGA Starter Kit User Manual
Page 11
Altera Corporation
2–1
July 2010
Preliminary
2. Development Board and
Control Panel Setup
Development
Board Setup
The development board is preloaded with an example design to
demonstrate the Cyclone
®
III device and board features. At power-up,
the preloaded design also enables you to quickly confirm that the board
is operating correctly.
Figure 2–1
shows the Cyclone III development board layout and
components.
Figure 2–1. Cyclone III Development Board Layout and Components
1-Mbyte SSRAM (U5)
DC Power
Input (J2)
Power Switch (SW1)
16-Mbyte
Parallel
Flash (U6)
USB
Connector
(J3)
Flash LED
USB
UART (U8)
JTAG Header (J4)
32-Mbyte
DDR SDRAM (U4)
Reconfigure
and Reset
Push Buttons
50-MHz
System Clock
User LEDs
User Push Button Switches
HSMC
Connector (J1)
Cyclone III Device (U1)
Configuration Done LED
Sense Resistor for FPGA
Core Power Measurement (JP6)
Sense Resistor
for Shared I/O
Power (JP3)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)