Altera User Flash Memory - Manual (Page 8)

Figure 5: IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
.qip - Lists files for synthesis
testbench - Simulation testbench files 1
- Testbench for supported simulators
.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
.sip - NativeLink simulation integration file
- Simulator setup scripts
- IP core variation files
.qip or .qsys - System or IP integration file
_generation.rpt - IP generation report
.bsf - Block symbol schematic file
.ppf - XML I/O pin information file
.spd - Combines individual simulation startup scripts
1
.html - Contains memory map
.sopcinfo - Software tool-chain integration file
_syn.v or .vhd - Timing & resource estimation netlist 1
.debuginfo - Lists files for synthesis
.v, .vhd, .vo, .vho - HDL or IPFS models
2
_tb - Testbench for supported simulators
_tb.v or .vhd - Top-level HDL testbench file
Parameter Settings
Table 9: ALTUFM_PARALLEL Parameters
Description Configuration Setting
You can select from the following options: Create a new custom IP core
variation, Edit an existing custom IP core variation, or Copy an existing
custom IP core variation. Which action do you want to
perform?
Select ALTUFM_PARALLEL from the Memory Compiler category. Select a IP core from the list
below
Specify the device family that you want to use. Which device family will you
be using?
Altera User Flash Memory (ALTUFM) IP Core User Guide Altera Corporation
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Parameter Settings 8
2014.08.18