Maxim Integrated DS80C390 - Manual (Page 21)

DS80C390
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During Stop mode the crystal oscillator is halted to maximize power savings. Typically 4 - 10 ms are
required for an external crystal to begin oscillating again once the device receives the exit stimulus. The
ring oscillator, by contrast, is a free-running digital oscillator that has no startup delay. The ring oscillator
feature is enabled by setting the Ring Oscillator Select bit, RGSL (EXIF.1). If enabled, the
microcontroller uses the ring oscillator as the clock source to exit Stop mode, resuming operation in less
than 100 ns. After 65536 oscillations of the external clock source (not the ring oscillator), the device will
clear the Ring Oscillator Mode bit, RGMD (EXIF.2) to indicate that the device has switched from the
ring oscillator to the external clock source.
The ring oscillator runs at approximately 10 MHz, but varies over temperature and voltage. As a result,
no serial communication or precision timing should be attempted while running from the ring oscillator
since the operating frequency is not precise. The default state exits Stop mode without using the ring
oscillator.
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write
operation. The Timed Access procedure prevents an errant processor from accidentally altering bits that
would seriously affect processor operation. The Timed Access procedure requires that the write of a
protected bit be immediately preceded by the following two instructions:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
Writing an AAh followed by a 55h to the Timed Access register (location C7h), opens a three-cycle
window that allows software to modify one of the protected bits. If the instruction that seeks to modify
the protected bit is not immediately preceded by these instructions, the write will be ignored. The
protected bits are:
WDCON.6 POR Power-On Reset Flag
WDCON.3 WDIF Watchdog Interrupt Flag
WDCON.1 EWT Watchdog Reset Enable
WDCON.0 RWT Reset Watchdog Timer
RCON.0 BGS Band-Gap Select
ACON.2 SA Stack Address Mode
ACON.1-0 AM1-AM0 Address Mode Select bits
MCON.7-6 IDM1-IDM0 Internal Memory Configuration and Location bits
MCON.5 CMA CAN Data Memory Assignment
MCON.3-0 PDCE3-PDCE.0 Program/Data Chip Enables
C0C.3 CRST CAN 0 Reset
C1C.3 CRST CAN 1 Reset
P4CNT.6 SBCAN Single Bus CAN
P4CNT.5-0 Port 4 Pin Configuration Control Bits
P5CNT.2-0 P5.7-P5.5 Configuration Control Bits
COR.7 IRDACK IRDA Clock Output Enable
COR.6-5 C1BPR7-C1BPR6 CAN 1 Baud Rate Pre-scale Bits
COR.4-3 C0BPR7-C0BPR6 CAN 0 Baud Rate Pre-scale Bits
COR.2-1 COD1-COD0 CAN Clock Output Divide Bit 1 and Bit 0
COR.0 CLKOE CAN Clock Output Enable