Cypress CY7C0430BV - Manual (Page 18)

CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B Page 18 of 37
Load and Read Address Counter [28]
Notes:
28. CE
0
= OE = LB = UB = V
IL
; CE
1
= R/W = CNTRST = MRST = MKLD = MKRD = V
IH
.
29. Address in output mode. Host must not be driving address bus after time t
CKLZ
in next clock cycle.
30. Address in input mode. Host can drive address bus after t
CKHZ
.
31. This is the value of the address counter being read out on the address lines.
Switching Waveforms (continued)
Read Data with Counter
t
SA
t
HA
t
SCLD
t
HCLD
t
SCINC t
HCINC
t
CH2
t
CL2
t
CYC2
Q
x–1
Q
x
Q
n
Q
n+1
Q
n+2
Read
Internal
Address
CLK
A
0
–A
15
CNTLD
DATA
OUT
CNTINC
A
n
t
SCRD
t
HCRD
CNTRD
A
n
A
n+1
A
n+2
INTERNAL
ADDRESS
A
n+2
A
n+2
A
n+2
Q
n+2
t
CD2
t
DC
t
CKLZ
t
CKLZ t
CKHZ
t
CKHZ
t
CA2
Load
External
Address
Note 29 Note 30
[31]
[+] Feedback