5 smarc sat30 special features, 1 watchdog timer, 1 cpld watchdog timer – Kontron SMARC-sAT30 User Manual
Page 67: 2 tegra t30 soc watchdog timer, 2 pmu gpio, Smarc sat30 special features, Watchdog timer, Cpld watchdog timer, Tegra t30 soc watchdog timer, Pmu gpio
User’s Guide
67
5
SMARC sAT30 Special Features
5.1
Watchdog Timer
The SMARC sAT30 module implements two Watchdog Timers (WDTs). Each one of these options is described below.
5.1.1 CPLD Watchdog Timer
[TBD. This feature is yet to be implemented. This is the functionality described by the SMARC Specification]
5.1.2 Tegra T30 SoC Watchdog Timer
NVIDIA’s Tegra T30 features an internal WDT. Kontron’s Linux kernel enables the internal T30 WDT and makes this
functionality available to users through the standard Linux Watchdog API.
A description of the API is available following the link below:
5.2
PMU GPIO
The PMU on the SMARC sAT30 contains a few GPIOs. These GPIOs are used for power management functionality but can
also be used for general purpose I/O. These GPIOs are different from SMARC sAT30 module hardware specification
GPIOs.
The table below shows the PMU GPIO usage information details:
TI PMU TPS659110C
SMARC sAT30 Edge finger
Net name
Notes
Pin #
Pin Name
Pin #
Pin Name
F1
SLEEP
S149
SLEEP#
CORE_PWR_REQ/
SLEEP_IN#
Default Function : Core power
enable signal
Alternate Function: Sleep
indication from carrier board
L3
INT1
PMU_INT#
PMU Interrupt signal
N1
PWRHOLD
S150
VIN_PWR_BAD#
POWER_HOLD/
VIN_PWR_BAD#
Power bad indication from
carrier board used as an option
to hold the PMU power output
with AND gate logic with
system reset.
N2
PWRDN
AP_OVERHEAT#
High Temp warning signal