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12 ethernet interface, 13 spi bus interface, Ethernet interface – Kontron COMe-cOHXX User Manual

Page 47: Spi bus interface

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Kontron COMe-cOH2/COMe-cOH6 User’s Guide

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The analog VGA graphics core, with a maximum resolution of 2560x1600x60Hz, is

integrated in the processor and is connected to the Com Express connector A-

B.

LVDS Flat Panel Interface (Type 6)

On modules with Type 6 COM Express connectors, the AMD processor has an

integrated LVDS 18-bit single channel. The processor LVDS channel A is

multiplexed to share two outputs; the 18-bit LVDS channel to COM Express LVDS

A and a Digital Display Interface (DDI) to COM Express DDI 2.

LVDS Flat Panel Interface (Type2)

On modules with Type 2 COM Express connectors, Display Port 0 (DP0) provides

24-bit, dual-channel, LVDS-to-COM Express LVDS channels A and B using an

Analogix ANX3110 DP-to-LVDS converter.

4.1.12

Ethernet Interface

The Ethernet interface on the COMe-cOH# COM is the Intel® 82574L GbE

Controller. Per the COM Express specification, the LAN magnetics are not on

the module. The GbE controller PHY is located close to the COM Express MDI

LAN interconnect pins to keep the MDI path short. The controller supports

auto-negotiation of 10/100/1000 Mbit connections.

The hardware supports S0, S3, or S5 power under BIOS to support WOL

(WakeOnLAN).

For cable lengths and termination on your baseboard, refer to the PICMG COM

Express® Design Guide on the PICMG website.

Configuration

The Ethernet controller is a PCI Express bus device. The BIOS allocates the

required system resources during the configuration of the PCIe device.

4.1.13

SPI Bus Interface

The Serial Peripheral Interface (SPI) signals are connected to the COM

Express connector A-B from the AMD Fusion Controller Hub. SPI BIOS is

supported at the maximum level the FCH supports, 16 MBytes. Two BIOS disable

straps, as defined in the COM Express Rev 2.0 specification, allow the

selection of either on-module SPI BIOS or carrier board SPI or LPC BIOS.

The SPI interface can be used to connect two carrier board devices, including

external BIOS flash memory. The implementation of this subsystem complies