Kontron COMe-bP5020 - Manual (Page 27)

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User Guide
COMe-bP5020
2.5.2 Signal Descriptions COM Express® Connectors
2.5.2.1 Ethernet (Group GigE MDI/GBE0 CTREF)
The COMe-bP5020 module provides one Gigabit Ethernet interface whose signals are already at copper wire Ethernet transmis-
sion voltage levels (physical levels / MDI) in accordance to the COM Express® Base Specification. So the carrier board needs
to add only the galvanic isolation (magnetics) function and the appropriate transmission connector type.
Additionally, for monitoring and control purposes, LED functionality is provided to indicate activity (GBE0_ACT#), Ethernet
link (GBE0_LINK#), Ethernet speed 100Mbit/s (GBE0_LINK100#) and Ethernet speed 1000Mbit/s (GBE0_LINK1000#).
A reference voltage for the carrier board Ethernet magnetics center tap (GBE0_CTREF) is not required.
2.5.2.2 Ethernet Management (ETH MGT)
The management communication between the Ethernet MACs and the external connected Ethernet PHYs is realized by using the
signal group ETH MGT. The CPU provides here two Ethernet management interface types (EMI1 and EMI2) which are dedicated
to the supported transfer speed.
EMI1 is the PHY management interface for 10/100/1000 Mbps transfer rates and is therefore dedicated to the dTSEC MACs of
the CPU.
EMI2 is the PHY management interface for 10Gbps transfer rates and is therefore dedicated to the XAUI interface of the CPU.
For a more detailed description of the Ethernet management interfaces refer to the CPU’s reference manual or the appropriate
IEEE standards (IEEE802.3: Part3, Clause 22 and Clause 45).
2.5.2.3 IEEE 1588
The Freescale™ QorIQ™ CPUs provide support for the Ethernet Precision Time Protocol (PTP) defined in the IEEE 1588 specifi-
cation. In order to utilize this functionality the CPUs provide additional IEEE 1588 time stamp signals. For a more detailed de-
scription of those signals please refer to the CPU’s reference manual.
2.5.2.4 Serial ATA
Two standard SATA interfaces are provided on the COM Express® connector. These signals are “ready-to-use” and can therefore
be routed directly to the SATA connectors/devices on the carrier.
2.5.2.5 SerDes
The signal group SerDes reflects all of the high speed low voltage differential signals provided by the CPU. The SerDes signals
are grouped into so called lanes and links.
A set of differential signal pairs, one pair for transmission and one pair for reception is called a lane. One or more lanes to-
gether form a link which can support various logical protocols such as: PCIe, sRIO, SGMI, XAUI, etc.
The P5020 Processor provides 18 lanes which are grouped into so called “banks” (Bank 1, Bank 2, Bank 3). Bank 1 consists of
10 lanes (Bank1 A-J), whereas Bank 2 and Bank 3 consist of 4 lanes each (Bank2 A-D and Bank3 A-D).
The logical protocols which run on the SerDes lanes are specified by the SRDS_PRTCL configuration value programmed into
the CPU at system power-up. To obtain a complete overview about all theoretical protocol combinations please refer to the
Freescale™ “P5020 QorIQ Integrated Multicore Communication Processor Family Reference Manual”, Chapter 3.5.11 SerDes
Lane Assignments and Multiplexing.
To handle the SerDes configuration in a more comfortable way, Kontron provides the configuration tool “sconf”. “sconf” pro-
vides a very easy way to configure the functionality of the SerDes lanes. Refer to Chapter 6, U-Boot for further information.