Kontron VSBC-32 - Manual (Page 38)

VSBC-32 Functional Description
ID 21168, Rev. 04 Page 2 - 6 © PEP Modular Computers GmbH
A schematic overview of all possible memory configurations is given in the figure on the
next page.
Figure 2-1: VSBC-32 Memory Configuration Variants
2.2.3 DMA Channels
Two independent channels are provided by the MC68(EN)360 controller chip and can
be used by applications requiring data transfer between VMEbus modules (as well as
CXC modules, if present), DRAM, flash memory and dual-ported SRAM.
Memory-to-memory transfers with the DMA’s of the MC68(EN)360 are possible with any
combination of on-board and VMEbus addresses.
DRAM
+
Flash
SRAM
2kbit EEPROM RTC
CPU/Serial
Comm.
Controller
Flash or
EPROM
(256kB or
1 MB)
Mainboard
- 1MB DRAM + 0 or 1 MB Flash EPROM
- 4MB DRAM + 1,2 or 4 MB Flash EPROM
- 8MB DRAM + 1,2 or 4 MB Flash EPROM
- 16MB DRAM + 1,2 or 4 MB Flash EPROM
- 32MB DRAM + 0.5,1 or 2 MB Flash EPROM
- 64MB DRAM + 1,2 or 4 MB Flash EPROM
Memory Piggybacks
or
VSBC-32E
MC68EN360
25MHz
33MHz
SRAM
256kB
SRAM
1MB
SRAM
256kB
VSBC-32
MC68360
25MHz
CPU Options