Kontron VSBC-32 - Manual (Page 36)

VSBC-32 Functional Description
ID 21168, Rev. 04 Page 2 - 4 © PEP Modular Computers GmbH
2.2 Specifics
2.2.1 System Control Functionality
Under the aspect of system control the on-chip 32-bit CPU core of the Motorola
MC68(EN)360 provides system integration at different processor frequencies. The pro-
cessor core acts essentially as a Motorola CPU32 microprocessor operating at 25MHz or
33MHz without cache memory. In addition, the MC68(EN)360 offers background debug-
ging via the on-chip “Background Debug Mode” which allows direct communication with
the CPU.
To act as a system controller, the VSBC-32(E) is provided with arbiter, system clock
driver, power monitor with system reset driver, IACK daisy chain driver and 7-level
VMEbus interrupt controller.
Arbitration is single-level FAIR (compare VME64 Specification Rule 3.14/Observation
3.17). If the VSBC-32(E) is used as a system controller and consequently placed in the
VMEbus backplane’s system slot, a special detection function provided by the board
makes any “slot 1” jumper setting superfluous. The VSBC-32(E) also provides a bus
monitor for the VMEbus.
Interrupt Control
The interrupt control logic of the MC68(EN)360 processes internal interrupt requests
alongside with external autovectored interrupt requests and a “mailbox” interrupt request
from the VMEbus control/status register. The interrupt control logic is built up using the
processor’s internal interrupt control and an external IRQ7 interrupt handler.
Internal requests are related to all interrupt requests caused by the controller sources,
including the processor’s system integration functions (watchdog timer, periodic inter-
rupt timer) and the communications processor module (RISC controller, timers, DMA’s,
SCC’s etc.).
In order to avoid conflicts regarding the different interrupt levels, it is recommended to
use IRQ level 4 for the MC68(EN)360 CPU internal requests and IRQ level 6 for the
MC68(EN)360 serial controller internal requests.
In addition, external interrupt sources can generate autovectored interrupts and an
external VMEbus master may require an interrupt by setting a “mailbox” IRQ in the
VMEbus control/status register.
For any detailled information as well as a complete list of the Motorola ® MC68(EN)360
controller signals please refer to the relating Data Sheet.