Achronix Speedster22i Memory PHY - Manual (Page 3)

UG043, April 26, 2014 3
Table of Contents
Copyright Info .................................................................................................... 2
Table of Contents .............................................................................................. 3
Overview ............................................................................................................ 4
DDR PHY ............................................................................................................ 7
Organization and Interfaces ................................................................................................... 7
PHY Structure and Operation .............................................................................................. 10
PHY – Controller Interfacing through Widebus .................................................................... 11
Byte Lane Building Blocks.................................................................................................... 12
TX, RX and OE paths in Data Bits ....................................................................................... 14
DQS Clocking and Circuitry ................................................................................................. 16
DLL Specs and Operation ............................................................................... 17
Revision History .............................................................................................. 20