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Mux output option ph0 ph1 – Achronix Speedster22i Memory PHY User Manual

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UG043, April 26, 2014

The MDLL uses a regulated supply generated by a high performance on-board regulator to
achieve the best possible performance in terms of jitter. It gets a clock as its reference to
generate desired delay in its delay cells. The delay cells used in its VCDL is based on a
current starved technique to provide the delay to generate the feedback signal. The phase of
the feedback signal is compared with the reference signal. This phase difference is translated
to voltage (PBIAS and NBIAS) by the phase detector and charge pump, which is given back
to the VCDL block to generate the required delay by either pushing out or pulling in the
feedback clock to reduce the phase error between the reference clock and the feedback clock.
The VCDL has 16 delay elements, and each delay cell provides 22.5 deg phase difference in
locked condition. As there are 16 delay cells in series, the out signal of the 16th delay cell will
have a 360 degrees phase offset with respect to the reference clock. Figure 11 below shows a
block diagram of the MDLL.

Delay Cell Block

ph360

Start-up

Phase detector

Charge Pump

Bias Generator

L

o

o

p

F

ilt

e

r

ph0

up

dn

Openloop_sel

Master
enable

PLL CLK

Front

buffer

16

th

Delay

cell

1

st

Delay

cell

Load

buffer

ph0

ph45

ph90

ph135

ph180

ph225

ph270

ph315

Pbias

Nbias

Figure 11: MDLL Block Diagram

The SDLL and the phase interpolator are used to adjust the delay of the strobe signal and
data signals in the data module so that they will be aligned. The phase interpolator gets 17
clocks with a phase separation of 22.5 degrees from the SDLL, and then performs fine tuning
by mixing various phases as determined by the programmable config bit settings. The phase
interpolator has two stages of mixing the clock. In the first stage it performs coarse tuning
through a mux by selecting the ph0 and ph1 option list as shown in Table 6.

Table 6: Phase Interpolator Mux Output List

Mux Output Option

Ph0

Ph1

1

0

22.5

2

22.5

45

3

45

67.5

4

67.5

90

5

90

112.5

6

112.5

135

7

135

157.5

8

157.5

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