Achronix Speedster22i Configuration - Manual (Page 6)

6 UG033, December 18, 2013
powering up VDDL. Otherwise, with SRAM cells powering up in unknown states, the
presence of one-hot muxes in the routing interconnect will undoubtedly mean that there will
be shorts leading to contention, and as a result unexpected behavior as far as current profiles
and draws.
This step can be bypassed as a debug or optimization step by asserting the
BYPASS_CLR_MEM pin/signal. This is really only acceptable/feasible if the application
involves re-configuring the FPGA without a power-down.
Once the memory clear is complete, the pin CONFIG_STATUS is released by the device, and
the weak external pull-up will pull this signal high to indicate that the FCU is ready to read
the bitstream.
It should be noted that only the configuration memory is cleared in this step. The embedded
BRAM and LRAM memory cells are NOT cleared and should be assumed to power up to
unknown states after configuration and in user mode. There is a separate option to preload
the memory contents using an initialization file.
Bitstream Sync and Device ID
: Speedster22i HD FPGA bitstreams always start
with a sync code which is pre-programmed to 0xAA55AA55. The sync code is always written
in the bitstream by the ACE software and is transparent to the user. Followed by sync, a
Device specific ID Code is checked to avoid programming the device with bitstream meant
for other devices. This is also a pre-programmed code provided by ACE.
Load Configuration Bits
: The configuration bitstream is a series of data words
which are ultimately made to internally form a bus and get shifted into a register chain
before being parallelly loaded into configuration memory frames in the FPGA fabric. There
are also command words which control whether the IO ring configuration registers or the
core configuration memory gets loaded.
The configuration file size and the configuration time are directly proportional to the number
of configuration memory frames that need to be programmed in the FPGA fabric. The
configuration file size is also dependent on the programming mode used, but strictly as a raw
hex file (see section on Bitstream File Generation Through ACE below) the bitstream size can
vary from <1MB for very small designs to close to 100MB for the largest designs that fill up
the entire FPGA and preload the BRAM memories.
CRC Check
: At the end of the bitstream, a CRC check is performed on the bitstream to
ensure that the data going into the configuration memory is error-free. This is disabled in
ACE for ES devices, but will be done by default on all production devices.
Startup Sequence
: After the configuration memory is programmed, the command
sequence to enter the user mode can be issued by the bitstream. Entering and exiting user
mode is controlled by a startup/shutdown state machine also implemented in the FCU. This
operates independently of the configuration state machine and so the configuration state
machine can process bitstream commands even after entering user mode.