Achronix Speedster22i Configuration - Manual (Page 19)

UG033, December 18, 2013 19
3. Lower VCCFHV_EFUSE[3:1], VCCRAM_EFUSE[3:1] and VDDA_NOM_E/W all back
down to 1.0V. Run phase 3 steps to validate the eFuse blowing process and return the
FCU back to a state to resume programming operations.
Once the eFuses are blown, the Speedster22iHD FPGA will be ready to accept encrypted
bitstreams as part of regular programming operation.