Achronix Speedster22i Configuration - Manual (Page 13)

UG033, December 18, 2013 13
JTAG
JTAG configuration and operation mode is independent of CONFIG_MODESEL settings,
although the recommendation is to ensure that the CONFIG_MODESEL values are one of
'100', '001', '010' or '000' to avoid unknown or illegal states.
The JTAG Tap controller design is compliant to the IEEE Std 1149.1. The TMS and TCK
inputs determine whether an instruction register scan or data register scan is performed.
TMS and TDI are sampled on the rising edge of TCK, while TDO changes on the falling edge.
Achronix recommends using an on-board JTAG header for Bitporter compatibility, direct
programming through the STAPL jam file (see Bitstream File Generation Through ACE
below) and the debug capability provided for Snapshot and SerDes debug in the PMA GUI.
JTAG configuration can be done for a Speedster22iHD device that in and of itself is the only
device in the JTAG scan chain, or is part of a series of devices all connected up in the chain.
Figure 8 below shows a block diagram of a single Speedster22iHD device in the JTAG scan
chain. Figure 9 shows the case where multiple devices are connected in series.
JTAG Header / Controller
Speedster22iHD FPGA
TCK
TMS
TRSTN
TDI
TDO
Figure 8: Single Speedster22iHD Device Connectivity to JTAG Header
Speedster22iHD
FPGA
JTAG Header / Controller
Device A Device B
T
C
K
T
M
S
T
R
S
T
N
T
D
I
T
D
O
T
C
K
T
M
S
T
R
S
T
N
T
D
I
T
D
O
T
C
K
T
M
S
T
R
S
T
N
T
D
I
T
D
O
TCK
TMS
TRSTN
TDI
TDO
Figure 9: Multiple Device Connectivity to JTAG Header