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Table 42. register summary (continued) – Cypress EZ-OTG CY7C67200 User Manual

Page 76

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CY7C67200

Document #: 38-08014 Rev. *G

Page 76 of 78

R/W

0xC0D6

SPI Data Port t

Reserved

xxxx xxxx

Data

xxxx xxxx

R/W

0xC0D8

SPI Transmit Address

Address...

0000 0000

...Address

0000 0000

R/W

0xC0DA

SPI Transmit Count

Reserved

Count...

0000 0000

...Count

0000 0000

R/W

0xC0DC

SPI Receive Address

Address...

0000 0000

...Address

0000 0000

R/W

0xC0DE

SPI Receive Count

Reserved

Count...

0000 0000

...Count

0000 0000

R/W

0xC0E0

UART Control

Reserved...

0000 0000

...Reserved

Scale
Select

Baud
Select

UART
Enable

0000 0111

R

0xC0E2

UART Status

Reserved...

0000 0000

...Reserved

Receive
Full

Transmit
Full

0000 0000

R/W

0xC0E4

UART Data

Reserved

0000 0000

Data

0000 0000

R

HPI Status Port

VBUS
Flag

ID
Flag

Reserved

SOF/EOP2
Flag

Reserved

SOF/EOP1
Flag

Reset2
Flag

Mailbox In
Flag

Resume2
Flag

Resume1
Flag

SIE2msg

SIE1msg

Done2
Flag

Done1
Flag

Reset1
Flag

Mailbox Out
Flag

Table 42. Register Summary

(continued)

R/W

Address

Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default High

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default Low

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