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Host n control register [r/w – Cypress EZ-OTG CY7C67200 User Manual

Page 20

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CY7C67200

Document #: 38-08014 Rev. *G

Page 20 of 78

Host n Control Register [R/W]

• Host 1 Control Register 0xC080

• Host 2 Control Register 0xC0A0

Figure 18. Host n Control Register

Register Description

The Host n Control register allows high-level USB transaction
control.

Preamble Enable (Bit 7)

The Preamble Enable bit enables or disables the transmission
of a preamble packet before all low-speed packets. This bit
should only be set when communicating with a low-speed
device.

1: Enable Preamble packet

0: Disable Preamble packet

Sequence Select (Bit 6)

The Sequence Select bit sets the data toggle for the next
packet. This bit has no effect on receiving data packets;
sequence checking must be handled in firmware.

1: Send DATA1

0: Send DATA0

Sync Enable (Bit 5)

The Sync Enable bit synchronizes the transfer with the SOF
packet in full-speed mode and the EOP packet in low-speed
mode.

1: The next enabled packet will be transferred after the SOF
or EOP packet is transmitted

0: The next enabled packet will be transferred as soon as the
SIE is free

ISO Enable (Bit 4)

The ISO Enable bit enables or disables an Isochronous trans-
action.

1: Enable Isochronous transaction

0: Disable Isochronous transaction

Arm Enable (Bit 0)

The Arm Enable bit arms an endpoint and starts a transaction.
This bit is automatically cleared to ‘0’ when a transaction is
complete.

1: Arm endpoint and begin transaction

0: Endpoint disarmed

Reserved

All reserved bits must be written as ‘0’.

Bit #

15

14

13

12

11

10

9

8

Field

Reserved

Read/Write

-

-

-

-

-

-

-

-

Default

0

0

0

0

0

0

0

0

Bit #

7

6

5

4

3

2

1

0

Field

Preamble

Enable

Sequence

Select

Sync

Enable

ISO

Enable

Reserved

Arm

Enable

Read/Write

R/W

R/W

R/W

R/W

-

-

-

R/W

Default

0

0

0

0

0

0

0

0

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