Switching characteristics – Cypress CY7C1443AV33 User Manual
Page 21
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Document #: 38-05357 Rev. *G
Page 21 of 31
Switching Characteristics
Over the Operating Range
Parameter
Description
–133
–100
Unit
Min.
Max.
Min.
Max.
t
POWER
V
DD
(Typical) to the first Access
1
1
ms
Clock
t
CYC
Clock Cycle Time
7.5
10
ns
t
CH
Clock HIGH
2.5
3.0
ns
t
CL
Clock LOW
2.5
3.0
ns
Output Times
t
CDV
Data Output Valid After CLK Rise
6.5
8.5
ns
t
DOH
Data Output Hold After CLK Rise
2.5
2.5
ns
t
CLZ
Clock to Low-Z
2.5
2.5
ns
t
CHZ
Clock to High-Z
3.8
0
4.5
ns
t
OEV
OE LOW to Output Valid
3.0
3.8
ns
t
OELZ
OE LOW to Output Low-Z
0
0
ns
t
OEHZ
OE HIGH to Output High-Z
3.0
4.0
ns
Setup Times
t
AS
Address Setup Before CLK Rise
1.5
1.5
ns
t
ADS
ADSP, ADSC Setup Before CLK Rise
1.5
1.5
ns
t
ADVS
ADV Setup Before CLK Rise
1.5
1.5
ns
t
WES
GW, BWE, BW
X
Setup Before CLK Rise
1.5
1.5
ns
t
DS
Data Input Setup Before CLK Rise
1.5
1.5
ns
t
CES
Chip Enable Setup
1.5
1.5
ns
Hold Times
t
AH
Address Hold After CLK Rise
0.5
0.5
ns
t
ADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
t
WEH
GW, BWE, BW
X
Hold After CLK Rise
0.5
0.5
ns
t
ADVH
ADV Hold After CLK Rise
0.5
0.5
ns
t
DH
Data Input Hold After CLK Rise
0.5
0.5
ns
t
CEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes
18. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD
(minimum) initially, before a read or write operation can be
initiated.
19. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of
on page 20. Transition is measured ± 200 mV
from steady-state voltage.
20. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.