Cirrus Logic CS5534-BS - Manual (Page 22)

CS5532/34-BS
22 DS755F3
2.2.4. Serial Port Interface
The CS5532/34’s serial interface consists of four
control lines: CS, SDI, SDO, SCLK. Figure 7 de-
tails the command and data word timing.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three wire interface.
SDI, Serial Data In, is the data signal used to trans-
fer data to the converters.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic. To accommodate optoisolators SCLK is
designed with a Schmitt-trigger input to allow an
optoisolator with slower rise and fall times to di-
rectly drive the pin. Additionally, SDO is capable
of sinking or sourcing up to 5 mA to directly drive
an optoisolator LED. SDO will have less than a
400 mV loss in the drive voltage when sinking or
sourcing 5 mA.
Command Time
8 SCLKs
Data Time 32 SCLKs
Write Cycle
CS
SCLK
SDI MSB
Command Time
8 SCLKs
CS
SCLK
SDI
Read Cycle
SDO MSB LSB
Command Time
8 SCLKs
8 SCLKs Clear SDO Flag SDO
SCLK
SDI
MSB LSB
Clock Cycles
t * d
CS
Data Time 32 SCLKs
Data Time 32 SCLKs
LSB
Data Conversion Cycle
/OWR MCLK
* td is the time it takes the ADC to perform a conversion. See the Single
Conversion and Continuous Conversion sections of the data sheet for more
details about conversion timing.
Figure 7. Command and Data Word Timing