Cirrus Logic CS5484 - Manual (Page 15)

CS5484
DS981F3 15
SDO
SDI
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
CS
SCLK
MSB
MSB
MSB-1
MSB-1
INTERMEDIATE BITS
INTERMEDIATE BITS
LSB
LSB
Figure 7. SPI Data and Clock Timing
TX
RX
t
9
t
11
CS
START LSB
LSB
DATA MSB STOP
START DATA MSB STOP
STOP IDLE OPTIONAL OVERLAP INSTRUCTION *
IDLE
t
10
IDLE
* Reading registers during the optional overlap instruction requires
the start to occur during the last byte transmitted by the part
Figure 8. Multi-Device UART Timing