Cirrus Logic CS4349 - Manual (Page 22)

22 DS782F2
CS4349
4.6.2 Control Port Mode
1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate
frequency, as discussed in Section 4.2 . In this state, the control port is reset to its default settings, VQ
will remain low, and VBIAS will be connected to VA.
2. Bring RST high. The device will remain in a low-power state with VQ low.
3. Perform a control port write to a valid register prior to the completion of approximately 192 LRCK
cycles in Single-Speed Mode (384 LRCK cycles in Double-Speed Mode, and 768 LRCK cycles in
Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 130 ms when
the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of
power-up timing.
4.7 Popguard Transient Control
The CS4349 uses a novel technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated
inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the
appropriate DC-blocking capacitors.
4.7.1 Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 192 sample periods, each output begins to ramp toward the quiescent
voltage. The amount of time it takes the outputs to ramp is related to the value of the DC-blocking capac-
itance and the output load. Using the example output circuit from
Figure 17 , the ramp up time will be ap-
proximately 0.25 seconds. When the ramp is complete, the outputs reach V
Q
and audio output begins.
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-
cent voltage, minimizing audible power-up transients.
Note the ramp up time varies due to internal factors, such as variance across device process, supply volt-
age, and die temperature corners as well as external output circuit component tolerances.
4.7.2 Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted that allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready
for the next power-on.
4.7.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.2 seconds.