Cirrus Logic CS4349 - Manual (Page 15)

DS782F2 15
CS4349
2.8 Switching Characteristics - Control Port - SPI Format
Inputs: Logic 0 = GND; Logic 1 = VLC; C
L
= 20 pF.
Notes: 10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For F
SCK
< 1 MHz.
12. CDOUT should not be sampled during this time.
Figure 9. Control Port Timing - SPI Mode
Table 9. Switching Characteristics - Control Port - SPI Format
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
sclk
- 6 MHz
RST Rising Edge to CS Falling t
srs
500 - ns
CCLK Edge to CS Falling (Note 10) t
spi
500 - ns
CS High Time Between Transmissions t
csh
1.0 - µs
CS Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 10) t
dh
15 - ns
Rise Time of CCLK and CDIN (Note 11) t
r2
- 100 ns
Fall Time of CCLK and CDIN (Note 11) t
f2
- 100 ns
Transition Time from CCLK to CDOUT Valid (Note 12) t
scdov
- 100 ns
Time from CS rising to CDOUT High-Z t
cscdo
- 100 ns
t r2 t f2
t dsu t dh
t sch t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs RST
CDOUT
t scdov t scdov t cscdo
Hi-Impedance