Cirrus Logic CS4341A - Manual (Page 29)

CS4341A
DS582F2 29
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
6. Only required for Quad-speed mode.
Parameters Symbol Min Max Units
MCLK Frequency 1.024 51.2 MHz
MCLK Duty Cycle 45 55 %
Input Sample Rate Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs 4
50
100
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle 40 60 %
SCLK Pulse Width Low t
sclkl
20 - ns
SCLK Pulse Width High t
sclkh
20 - ns
SCLK Frequency MCLKDIV Disabled
-
Hz
MCLKDIV Enabled
-
Hz
SCLK rising to LRCK edge delay t
slrd
20 - ns
SCLK rising to LRCK edge setup time t
slrs
20 - ns
SDIN valid to SCLK rising setup time t
sdlrs
20 - ns
SCLK rising to SDIN hold time t
sdh
20 - ns
SCLK rising to MCLK edge delay ( NOTE 7 ) t
smd
8 - ns
MCLK
2
------------------
MCLK
4
------------------
t
s m d
t
s lrd
t
s lrs t
s c lk l
t
s c lk h
t
s d lrs
t
s d h
M C L K
L R C K
S C L K
S D A T A
Figure 18. Serial Input Timing