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Register description, L port register 5.1. in, Register 5.1. in this state, the cs4341a – Cirrus Logic CS4341A User Manual

Page 17: Section 5.1.1 for implementation deta, Cs4341a

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CS4341A

DS582F2

17

5.

REGISTER DESCRIPTION

NOTE: All registers are read/write in I

2

C mode and write only in SPI mode, unless otherwise stated.

5.1

MODE CONTROL 1 (ADDRESS 00H)

5.1.1 SPEED MODE CONTROL (MC)

BIT 5-6

Default = 00
00 - Single-Speed Mode
01 - Double-Speed Mode
10 - Quad-Speed Mode

The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These
bits are ignored if the auto-detect defeat is disabled (AUTOD = 0).

5.1.2 AUTO-DETECT DEFEAT (AUTOD)

BIT 2

Default = 0
0 - Disabled
1 - Enabled

The Auto-Detect function can be defeated to allow sample rate changes from 50 to 84 kHz, and from
100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section
5.1.1) if the auto-detect feature is defeated.

5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV)

BIT 1

Default = 0
0 - Disabled
1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

5.2

MODE CONTROL 2 (ADDRESS 01H)

7

6

5

4

3

2

1

0

Reserved

MC1

MC0

Reserved

Reserved

AUTOD

MCLKDIV

Reserved

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

AMUTE

DIF2

DIF1

DIF0

DEM1

DEM0

POR

PDN

1

0

0

0

0

0

1

1