Test configurations, Design considerations, Austin minilynx – GE Industrial Solutions Austin Minilynx SIP User Manual
Page 10: Input filtering, Lineage power 10, Figure 26. output ripple and noise test setup, The austin minilynx
Data Sheet
October 2, 2009
Austin MiniLynx
TM
SIP Non-isolated Power Modules:
2.4 – 5.5Vdc input; 0.75Vdc to 3.63Vdc Output; 3A output current
LINEAGE
POWER
10
Test Configurations
TO OSCILLOSCOPE
CURRENT PROBE
L
TEST
1μH
B
A
TTE
R
Y
C
S
1000μF
Electrolytic
E.S.R.<0.1
Ω
@ 20°C 100kHz
2x100μF
Tantalum
V
IN
(+)
COM
NOTE: Measure input reflected ripple current with a simulated
source inductance (L
TEST
) of 1μH. Capacitor C
S
offsets
possible battery impedance. Measure current as shown
above.
C
IN
Figure 25. Input Reflected Ripple Current Test
Setup.
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
V
O
(+)
COM
1uF
.
RESISTIVE
LOAD
SCOPE
COPPER STRIP
GROUND PLANE
10uF
Figure 26. Output Ripple and Noise Test Setup.
V
O
COM
V
IN
(+)
COM
R
LOAD
R
contact
R
distribution
R
contact
R
distribution
R
contact
R
contact
R
distribution
R
distribution
V
IN
V
O
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
Figure 27. Output Voltage and Efficiency Test Setup.
η =
V
O
. I
O
V
IN
. I
IN
x
100
%
Efficiency
Design Considerations
Input Filtering
The Austin MiniLynx
TM
SIP module should be connected
to a low-impedance source. A highly inductive source
can affect the stability of the module. An input
capacitance must be placed directly adjacent to the
input pin of the module, to minimize input ripple voltage
and ensure module stability.
To minimize input voltage ripple, low-ESR polymer and
ceramic capacitors are recommended at the input of the
module. Figure 28 shows the input ripple voltage
(mVp-p) for various outputs with 1x22µF (TDK:
C3225X5R0J226V) ceramic capacitor at the input of the
module. Figure 29 shows the input ripple with 1x47µF
(TDK: C3225X5R0J476M) ceramic capacitor at full load.
Input
Ri
ppl
e
Vol
tage (mVp-
p
)
0
20
40
60
80
100
120
140
160
0
0.5
1
1.5
2
2.5
3
3.5
3.3Vin
5Vin
Output
Voltage
(Vdc)
Figure 28. Input ripple voltage for various outputs
with 1x22 µF ceramic capacitor at the input (full-
load).
Input
Ri
ppl
e
Vol
tage (m
Vp-p)
0
20
40
60
80
100
120
140
160
0
0.5
1
1.5
2
2.5
3
3.5
3.3Vin
5Vin
Output
Voltage
(Vdc)
Figure 29. Input ripple voltage for various outputs
with 1x47 µF ceramic capacitor at the input (full
load).