Rainbow Electronics BR24C21FV - Manual (Page 7)

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
2) Bi-directional Mode
START CONDITION
•All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
•The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this condition has been met.
STOP CONDITION
•All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH.
•The stop condition initiates internal write cycle to write the data into memory array after write sequence.
•The stop condition is also used to place the device into the standby power mode after read sequence.
•A stop condition can only be issued after the transmitting device has released the bus.
DEVICE ADDRESSING
•Following a START condition, the master output the device address of the slave to be accessed. The most significant
four bits of the slave address are the “device type indentifier”, For the BR24C21, BR24C21F, BR24C21FJ and
BR24C21FV this is fixed as “1010”.
•The next three bits of the slave address are don’t care.
•The last bit of the stream determines the operation to be performed. When set to “1”, a read operation is selected ;
when set to “0”, a write operation is selected.
R / W set to “0” ··· WRITE
(This bit also sets to “0” for random read operation)
R / W set to “1” ··· READ
∗ ∗ ∗ 1010 R / W
∗ Don't care
WRITE PROTECT FUNCTION
•WRITE ENABLE (VCLK)
When using the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV in the Bi-directional Mode, the VCLK pin can
be used as a write enable pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents
writing to any location in the array. Changing VCLK from high to low during the self-timed program operation will not
halt programming of the device. Setting VCLK low allow the word address setting in random read.