Rainbow Electronics AT86RF230 - Manual (Page 14)

14
AT86RF230
5131A-ZIGB-06/14/06
micro-controller. An additional 256 µs timer ensures that frequency stability is sufficient to drive filter tuning (FTN)
and the PLL. After band-gap voltage and digital voltage regulator settling, the transceiver enters the TRX_OFF
state and waits for further commands.
0 600 500 700
Active Blocks
800 900 1000 1100
FTN BG DVREG AVREG 16
s
PLL Timer 256 s Timer 128 s
TRX_OFF State PLL_ON
Command
PLL_ON,
RX_ON
SLP_TR=0
XOSC
Timer 128 s
VDD on
XOSC
TRX_OFF
Typical block settling time, stays on
Block active
waiting for SPI commands
P_ON
XOSC delivers
clock CLKM delivers
clock Clock
stable IRQ
PLL locked
Signals/Events
RX_ON
RX_ON SLEEP
RST=0 Pin
CLKM_CTRL
~400
Time [µs]
Time [µs]
µ µ µ µ µ µ µ µ µ µ µ µ
µ µ µ µ
Figure 4-2. Wake-up Procedure from SLEEP Mode and P_ON Mode to RX_ON Mode (PLL locked)
Forcing PLL_ON mode or RX_ON mode initiates a ramp-up sequence of the analog voltage regulator followed by a
16 µs timer. This timer makes sure that the analog 1.8V supply is stabilized before enabling PLL circuitry. RX_ON
mode can be forced any time during PLL_ON mode regardless of the PLL lock signal.
When the wake-up sequence is started from P_ON mode (VDD first applied to the IC) the state machine will stop
after the 128 µs timer to wait for a valid TRX_OFF command from the micro-controller. The default CLKM
frequency value in P_ON mode is 1 MHz. At this rate, an SPI access requires approximately 38 µs. The SPI
programming in synchronous mode can be speeded up by setting the frequency of the clock output at pin CLKM in
register 0x03 (TRX_CTRL_0) to the maximum value allowed.
If a chip reset with 0 RST = is generated, the sequence starts with filter tuning (FTN) as indicated in Figure 4-2.
4.3.2. Transition from PLL_ON via BUSY_TX to RX_ON
PLL
Timer 14 2
Command
SLP_TR=0
PLL settling to Tx frequency
PA
ramp
BUSY_TX PLL_ON
Active Blocks
State
0 10 16
Transmitting frame
PLL_ON
Time [µs]
Timer 32
PLL settling to Rx frequency
x x+32
Pin
TX_ START
PLL
RX_ON
RX_ON
Typical block settling time, stays on
Block active
waiting for SPI commands
Time [µs] s µ µ µ µ s µ µ µ µ s µ µ µ µ
Figure 4-3. Switching from TX to RX
The time scale in Figure 4-3 is relative to TX frame start.