Rainbow Electronics AT45DB161E - Manual (Page 60)

60 Adesto AT45DB161E [DATASHEET]
8782D–DFLASH–11/2012
Figure 25-10. Status Register Read (Opcode D7h)
Figure 25-11. Manufacturer and Device Read (Opcode 9Fh)
Figure 25-12.Reset Timing
Note: 1. The CS signal should be in the high state before the RESET signal is deasserted.
SCK
CS
SI
SO
MSB
2 3 1 0
1 1 0 1 0 1 1 1
6 7 5 4 10 11 9 8 12 21 22 17 20 19 18 15 16 13 14 23 24
Opcode
MSB MSB
D D D D D D D D D D
MSB
D D D D D D D D
Status Register Data Status Register Data
High-impedance
SCK
CS
SI
SO
6 0
9Fh
8 7 46
Opcode
1Fh 00h 01h 00h
Manufacturer ID Device ID
Byte 1
Device ID
Byte 2
EDI
String Length
EDI
Data Byte 1
High-impedance
14 16 15 22 24 23 38 40 39 30 32 31
Note: Each transition shown for SI and SO represents one byte (8 bits)
26h
CS
SCK
RESET
SO (Output)
High Impedance High Impedance
SI (Input)
tRST
tREC tCSS