Rainbow Electronics AT84AD004 - Manual (Page 47)

47
AT84AD004
5390A–BDC–06/04
TRDR Data Ready Reset
Delay The delay between the falling edge of the Data Ready output asynchronous reset signal
(DDRB) and the reset to digital zero transition of the Data Ready output signal (DR)
TS Settling Time The time delay to rise from 10% to 90% of the converter output when a full-scale step
function is applied to the differential analog input
VSWR Voltage Standing
Wave Ratio The VSWR corresponds to the ADC input insertion loss due to input power reflection. For
example, a VSWR of 1.2 corresponds to a 20 dB return loss (99% power transmitted and 1%
reflected)
Table 14. Definitions of Terms (Continued)
Abbreviation Definition Description