Rainbow Electronics AT84AD004 User Manual
Page 21
21
AT84AD004
5390A–BDC–06/04
CLKQN
128
Inverted phase (-) clock input signal
(CLKQ)
DDRB
126
Synchronous data ready reset I and Q
DDRBN
127
Inverted phase (-) of input signal (DDRB)
DOAI0, DOAI1, DOAI2, DOAI3, DOAI4,
DOAI5, DOAI6, DOAI7
117, 113, 105, 101, 93, 89, 81, 77
In-phase (+) digital outputs first phase
demultiplexer (channel I) DOAI0 is the
LSB. D0AI7 is the MSB
DOAI0N, DOAI1N, DOAI2N, DOAI3N,
DOAI4N, DOAI5N, DOAI6N, DOAI7N,
118, 114, 106, 102, 94, 90, 82, 78
Inverted phase (-) digital outputs first
phase demultiplexer (channel I) DOAI0N
is the LSB. D0AI7N is the MSB
DOBI0, DOBI1, DOBI2, DOBI3, DOBI4,
DOBI5, DOBI6, DOBI7
119, 115, 107, 103, 95, 91, 83, 79
In-phase (+) digital outputs second phase
demultiplexer (channel I) DOBI0 is the
LSB. D0BI7 is the MSB
DOBI0N, DOBI1N, DOBI2N, DOBI3N,
DOBI4N, DOBI5N, DOBI6N, DOBI7N
120, 116, 108, 104, 96, 92, 84, 80
Inverted phase (-) digital outputs second
phase demultiplexer (channel I) DOBI0N
is the LSB. D0BI7N is the MSB
DOAQ0, DOAQ1, DOAQ2, DOAQ3,
DOAQ4, DOAQ5, DOAQ6, DOAQ7
136, 140, 4, 8, 16, 20, 28, 32
In-phase (+) digital outputs first phase
demultiplexer (channel Q) DOAI0 is the
LSB. D0AQ7 is the MSB
DOAQ0N, DOAQ1N, DOAQ2N, DOAQ3N,
DOAQ4N, DOAQ5N, DOAQ6N, DOAQ7N
135, 139, 3, 7, 15, 19, 27, 31
Inverted phase (-) digital outputs first
phase demultiplexer (channel Q) DOAI0N
is the LSB. D0AQ7N is the MSB
DOBQ0, DOBQ1, DOBQ2, DOBQ3,
DOBQ4, DOBQ5, DOBQ6, DOBQ7
134, 138, 2, 6, 14, 18, 26, 30
In-phase (+) digital outputs second phase
demultiplexer (channel Q) DOBQ0 is the
LSB. D0BQ7 is the MSB
DOBQ0N, DOBQ1N, DOBQ2N,
DOBQ3N, DOBQ4N, DOBQ5N,
DOBQ6N, DOBQ7N
133, 137, 1 ,5, 13, 17, 25, 29
Inverted phase (-) digital outputs second
phase demultiplexer (channel Q)
DOBQ0N is the LSB. D0BQ7N is the MSB
DOIRI
75
In-phase (+) out-of-range bit input
(I phase) combined demultiplexer
out-of-range is high on the leading edge of
code 0 and code 256
DOIRIN
76
Inverted phase of output signal DOIRI
DOIRQ
34
In-phase (+) out-of-range bit input
(Q phase) combined demultiplexer
out-of-range is high on the leading edge of
code 0 and code 256
DOIRQN
33
Inverted phase of output signal DOIRQ
MODE
74
Bit selection for 3-wire bus interface or
nominal setting
CLK
73
Input clock for 3-wire bus interface
DATA
72
Input data for 3-wire bus
LND
71
Beginning and end of register line for
3- wire bus interface
CLKOI
121
Output clock in-phase (+) channel I
Table 8. AT84AD004 LQFP 144 Pin Description (Continued)
Symbol
Pin number
Function