Rainbow Electronics AT84AD004 - Manual (Page 17)

17
AT84AD004
5390A–BDC–06/04
Figure 11. Data Ready Reset
Figure 12. Data Ready Reset 1:1 DMUX Mode
Note: The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset
occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then
only, remains in reset state (frozen to a low level in 1:1 DMUX mode). The next falling edge of the input clock after reset makes
the output clock return to normal mode (after TDR).
DDRB
CLKI or
CLKQ
500 ps
ALLOWED ALLOWED
FORBIDDEN FORBIDDEN
1 ns min
500 ps
1 ns min
CLKI or
CLKQ
CLKOI or
CLKOQ
DOIA[0:7] or
DOQA[0:7]
VIN
TA
N
N
DDRB
2 ns
TDR
TDR
Pipeline Delay + TDO
Clock in
Reset
N + 1