Rainbow Electronics MAX17047 - Manual (Page 25)

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MAX17047
ModelGauge m3 Fuel Gauge
Figure 33. MiscCFG Register Format (Input)
LearnCFG Register (28h)
The LearnCFG register controls all functions relating
to adaptation during operation. The LearnCFG register
default values should not be changed unless specifically
required by the application.
Figure 32 is the LearnCFG
register format:
0—Bit must be written 0. Do not write 1.
1—Bit must be written 1. Do not write 0.
Filt Empty—Empty Detect Filter. This bit selects whether
empty is detected by a filtered or unfiltered voltage read-
ing. Setting this bit to 1 causes the empty detection algo-
rithm to use the AverageV
CELL
register. Setting this bit to
0 forces the empty detection algorithm to use the V
CELL
register. This bit is written to 0 at power-up.
LS2:LS0—Learn Stage. See
Figure 3 The Learn Stage
value controls the influence of the VFG on the mixing
algorithm. At power-up, Learn Stage defaults to 0h, mak-
ing the voltage fuel gauge dominate. Learn Stage then
advances to 7h over the course of two full cell cycles to
make the coulomb counter dominate. Host software can
write the Learn Stage value to 7h to advance to the final
stage at any time. Writing any value between 1h and
6h is ignored. Learn Stage reflects the D5, D6, and D7
bits of the Cycles register. Update the Cycles register
to advance to an intermediate state. For example, set
Cycles = 160% to advance to Learn Stage 5.
MiscCFG Register (2Bh)
The MiscCFG control register enables various other
functions of the device. The MiscCFG register default
values should not be changed unless specifically
required by the application.
Figure 33 is the MiscCFG
register format:
0—Bit must be written 0. Do not write 1.
1—Bit must be written 1. Do not write 0.
X—Don’t Care. Bit may read 0 or 1.
SACFG1:SACFG0—SOC Alert Config. SOC Alerts can
be generated by monitoring any of the SOC registers as
follows. SACFG defaults to 00 at power-up:
0 0 SOC Alerts are generated based on the SOC
REP
register.
0 1 SOC Alerts are generated based on the SOC
AV
register.
1 0 SOC Alerts are generated based on the SOC
MIX
register.
1 1 SOC Alerts are generated based on the SOC
VF
register.
Figure 32. LearnCFG Register Format (Input/Output)
MSB—ADDRESS 2Bh LSB—ADDRESS 2Bh
0 0 X X enBi1 0 MR 4 MR 3 MR 2 MR 1 MR 0 1 0 0
SACFG
1
SACFG
0
MSb LSb MSb LSb
MR 0 UNITS: 6.25µV
MSB—ADDRESS LSB—ADDRESS
0 0 1 0 0 1 1 0 0 LS 2 LS 1 LS 0 1
Filt
Empty
1 1
MSb LSb MSb LSb